Introduction to Digital Design and Integrated Circuits
EECS 151 Introduction to Digital Design and Integrated Circuits 3 Units
EECS 251A Introduction to Digital Design and Integrated Circuits 3 Units
Faculty in charge: Prof. J. Rabaey
Terms offered: 2016 Spring, 2015 Fall
Catalog description:
An introduction to digital and system design. The material provides a top-down view of the principles, components, and methodologies for large scale digital system design. The underlying CMOS devices and manufacturing technologies are introduced, but quickly abstracted to higher-levels to focus the class on design of larger digital modules for both FPGAs (field programmable gate arrays) and ASICs (application specific integrated circuits). The class includes extensive use of industrial grade design automation and verification tools for assignments, labs and projects.
The class has two lab options: ASIC Lab (EECS 151LA) and FPGA Lab (EECS 151LB). Students must enroll in at least one of the labs concurrently with the class.
EECS 151LA Application Specific Integrated Circuits Laboratory 2 Units
Faculty in charge: V. Stojanovic
Terms offered: 2016 Spring, 2015 Fall
Catalog description:
This lab lays the foundation of modern digital design by first presenting the scripting and hardware description language base for specification of digital systems and interactions with tool flows. The labs are centered on a large design with the focus on rapid design space exploration. The lab exercises culminate with a project design, e.g., implementation of a three-stage RISC-V processor with a register file and caches. The design is mapped to simulation and layout specification.
Number of students in lab: 19
EECS 151LB Field-Programmable Gate Array Laboratory 2 Units
Terms offered: 2016 Spring, 2015 Fall
This lab covers the design of modern digital systems with Field-Programmable Gate Array (FPGA) platforms. A series of lab exercises provide the background and practice of digital design using a modern FPGA design tool flow. Digital synthesis, partitioning, placement, routing, and simulation tools for FPGAs are covered in detail. The labs exercises culminate with a large design project, e.g., an implementation of a full three-stage RISC-V processor system, with caches, graphics acceleration, and external peripheral components. The design is mapped and demonstrated on an FPGA hardware platform.
Number of students in lab: 4
Labs are held in 125 Cory
Stations C125M-1 to C125M-21 (21 stations)